The present invention lies in the field of active power management (APM) which means the short term control of processor clock frequencies and core supply voltage (Vdd) to minimise power consumption in an active mode. Active power management is generally handled by a fast power management component, where clock frequencies and voltages may need to be modified every few hundred microseconds. Decisions are based on short term application needs.
Many computing systems are required to run at particular speeds in order to function correctly. For example, a processor in a mobile terminal of a wireless communication network is required to operate at a particular speed in order to process call data in real-time to allow an operator of the terminal to engage in real-time communications with another person, without dropping the call. This is just one example of a computing system which is required to operate at a particular speed. In order to operate at the particular speed, the frequency of the clock signal used in the computing system is required to be at least a particular threshold value.
In order for a computing system to operate at high clock frequencies, a correspondingly high supply voltage is required. However, as the supply voltage used in the computing system increases, so does the power used by the computing system, which is disadvantageous. It is desirable to keep the supply voltage low, but not too low such that the computing system cannot operate at the required clock frequency.
Automatic tracking software can be used to select a required supply voltage for use in a computing system. For example an AVS (Automatic Voltage Scaling) function can be used to select the supply voltage.
The supply voltage is set in an attempt to accommodate the software that is running on the computing system. Specifically, as the software is executed the supply voltage will fluctuate as the supply current drawn as a consequence of the operations of the executed software can vary more quickly than the supply voltage regulator circuit can react. Such changes in supply voltage are known as supply ‘bouncing’, ‘droop’ ‘transient response’ or simply ‘noise’. The voltage regulator circuit and its connection to the computing system will contain inductive and capacitive components and thus will have resonant frequencies which can increase the effect of the voltage ‘bouncing’ if the software happens to cause load transients at frequencies that excite these resonances. If the supply voltage becomes too low then logic in a critical timing path of the computing system can fail and some circuits can fail to work at any speed. For example WRITE operations, particularly to 6 transistor Static Random Access Memory (SRAM) cells, can be very susceptible to failure under low supply voltage conditions.
In order to avoid the failure of a critical path in the computing system, a voltage margin is implemented, such that in normal operating conditions the supply voltage is set slightly higher (by an amount that is the voltage margin) than the minimum voltage required in the critical path at the current clock frequency. This voltage margin allows the voltage to droop slightly as the software is operated without going below the minimum required to prevent the critical path from failing. The voltage margin is typically chosen to cover manufacturing and the software variability (i.e. a software factor). The voltage margins are chosen to be at a level that is considered ‘safe’ for any part in the critical path of the computing system at a particular speed.
The additional voltage margin increases the power consumption of the computing system in operation.